The present invention generally relates to integrated circuits, and more specifically, to a function block architecture for application specific integrated circuits (ASICs).
Use of ASICs (application specific integrated circuits) has become widespread in the semiconductor industry as giving circuit design engineers a relatively high amount of functionality in a relatively small package. In particular, ASICs are customizable integrated circuits that are customized to implement a circuit specified by a design engineer (a xe2x80x9cuser-defined circuitxe2x80x9d). The term xe2x80x9cASICxe2x80x9d actually refers to a variety of integrated circuit (IC) styles that vary in degree of customizability, including standard cells, module based arrays, and gate arrays. As a general rule, the more customization that is required, the more expensive the ASIC will be and the longer the ASIC will take to fabricate and/or customize.
ASICs, such as gate arrays and module based arrays, generally include an array of function blocks, where each function block is predesigned and/or prefabricated to include a particular number, arrangement, and type of semiconductor devices, e.g., transistors. To customize the ASIC to implement a particular user-defined circuit, various connections are made among the semiconductor devices within the function block and/or various connections are made among function blocks (i.e., although the semiconductor devices are fixed in size and position, routing is customized).
In forming ASICs generally, several layers will be required. FIG. 1 shows a cross-sectional view of a generic integrated circuit. First, active layers are formed on a semiconductor substrate. The active layers 110 include devices such as transistors and diodes. Most active layer devices are formed independently of one another, i.e., they are not connected to form a circuit. Thus, once active layers 110 are formed, conducting layers, which are often composed of a metal such as aluminum or copper but can be formed with other conductors, are formed over the active layers to interconnect the devices, thereby forming a circuit. Several conducting layers may be required to completely interconnect the devices to form a useful circuit. Four metal layers, M1120, M2130, M3140, and M4150, are shown in FIG. 1. Of course, different types of ICs may require more or less than four metal layers for circuit interconnection.
In between each conducting layer is an insulating layer 115, 125, 135, 145 as shown in FIG. 1. Insulating layers are present to prevent shorts between conducting layers. To interconnect the conducting layers, vias 116 are formed through the insulating layers.
In forming the structure of FIG. 1, after the active layers 110 are formed, an insulating layer 115 is formed over the active layers 110, for instance, by growth or deposition of insulating material. Next, a masking step is utilized to form vias in the insulating layer, as is generally known in the art. Such masking often entails depositing a photoresist layer and patterning the layer using ultra-violet light, enabling removal of only selected portions of the photoresist, and then etching the insulating layer in accordance with the photoresist pattern. After forming the vias, a conducting layer is deposited and then patterned using a similar masking process, so that metal (or other conductor) remains only in desired locations. The process is repeated for each insulating layer and conducting layer required to be formed.
Thus each conducting layer required to be formed generally demands at least two masking steps: one step to form vias through the insulating layer to connect to the layerbelow and one step to form connection wires or lines. Unfortunately, each mask step required generally entails significant time and expense.
At the active layer level, ASIC active devices are generally arranged to form an array of function blocks, also commonly referred to as cells or modules. To interconnect active devices within each function block (i.e., form xe2x80x9clocal interconnectionsxe2x80x9d) a series of horizontal and vertical connection lines formed in the conducting layers are utilized. As is well understood in the art, any two points can be connected using a series of horizontal and vertical connection lines. While such local interconnections can be done in one metal layer, more typically, horizontal connections are formed in a first metal layer and vertical connections are formed in a second metal layer with an insulating layer having vias formed between.
Of great importance to an IC designer in implementing circuit designs with an ASIC is the functionality available from the ASIC. That is, the IC designer may have circuit designs which include a large number of different combinational functions (e.g., Boolean logic), sequential functions (e.g., flip-flops, latches), and/or memory functions (e.g., SRAM), and the designer would prefer an ASIC which efficiently implements a significant majority of his or her design so that the overall design is implemented in the smallest space possible. Since ASICs are generally formed of an array of function blocks, the functionality available in each of these devices will be primarily determined by the architecture within each function block or module.
Also important to an IC designer is customization time. Particularly during the design stages, the IC designer wants to obtain a model, or prototype, of his or her designs quickly so that the designs can be tested and used with other circuitry.
One approach to gate arrays is to create a function block with primarily freestanding transistors, that is, transistors that have few, if any, internal connections to one another within the function block, sometimes referred to as a xe2x80x9csea of gates.xe2x80x9d The transistors within such a function block often vary in size and drive capability with respect to one another to aid in achieving various functions.
In order to customize a sea-of-gates type architecture, routing of connections between the transistors within the function block as well as those formed between function blocks must be undertaken to implement a user-defined circuit. There are generally three to five layers of connecting wires formed over the transistor layer, and each layer requires at least two masking steps to form (one step to form vias to the layer below and one step to form connecting wires). Thus, six to ten masking steps must be undertaken to fully customize a sea-of-gates type gate array. So although this approach allows for circuit flexibility by allowing for implementation of combinational and sequential functions, as well as memory functions, such an approach will bear additional costs due to multiple masking and routing steps. In addition, because of the multiple masking steps required, production time for customizing the gate array can be considerable.
A second approach to gate arrays, and one having a more rapid customization time, is field programmable gate arrays (FPGAs). The function block configuration in an FPGA is often composed of a fixed circuit of multiplexers and other logic gates and is usually arranged such that varying the input signals to the function block will form various useful functions. Thus, to customize an FPGA, an IC designer can specify signals to be coupled to the inputs and outputs for each function block.
FPGA customization time tends to be more rapid than other types of gate arrays because the transistor layer and all connection layers (all vias and wires) are fixed. Also fixed and in between the function blocks in the array is an interconnect structure formed of a plurality of intersecting wires. At each intersection is either a fuse or a programmable RAM bit. Thus, to program function-block functionality (i.e., to control input signals to each function block), either a fuse is stressed to melt and form a connection at the intersection, or a RAM bit is programmed to form this connection. Since the entire FPGA structure is fixed by the manufacturer, no additional mask steps are required and FPGA programming can actually be done by the IC designer with equipment and software at his or her own place of business. Commonly, an IC designer will specify a function (often from a library) that the designer wishes the function block to perform and the signals to be coupled to function block inputs and outputs are then determined and programmed by software.
Despite rapid and easy customization, FPGAs currently available have drawbacks. First, FPGAs are often used in intermediate design steps for test purposes, but cannot often be used in a final product: because of the nature of the FPGA interconnect structure, an FPGA often will not meet the performance expectations of the final product (e.g., timing) and thus has only limited use in test situations.
Second, few, if any, FPGA manufacturers have developed a function block architecture which can fully support the functionality (e.g., combinational, sequential, and memory functions) required by an IC designer. Almost all FPGA producers produce function blocks capable of implementing a variety of combinational circuits (e.g., Boolean functions). A few FPGA suppliers in addition to providing circuits capable of combinational logic, will also provide distinct function blocks for sequential logic (e.g., flip-flops, latches) spaced periodically throughout the FPGA array. While providing the designer with periodic function blocks for sequential function support is helpful, these sequential function blocks may not be in an ideal location with respect to other function blocks (e.g., those supporting combinational functions), may not occur often enough to adequately support IC designs, and particularly may be less than ideal with respect to routing, timing, and other placement issues. Moreover, a user will typically not be able to select the output drive strength of a particular function block, which may cause loading problems in certain circumstances.
Other FPGA providers provide function blocks which can support both combinational and sequential functions. However, these function blocks are usually designed so that the circuitry supporting each of these function types is separate and distinct within the function block. While providing more options to the designer, this approach will significantly limit gate arrays in size since each function block takes up considerably more space in accommodating distinct circuitry to support each function type.
As IC designers create more and more complex IC designs, they are demanding more functional capabilities from gate arrays while further demanding that customization time remain low, that gate array die size remain small, and that device reliability remain high. So, although available gate arrays allow some flexibility to the IC designer, improved architectures are always desirable. Particularly desirable is any architectural design that allows increased flexibility and functionality while reducing customization time.
The present disclosure describes an ASIC having an array of predesigned function blocks that can implement a user-defined circuit, that will allow any function block to be used for combinational and/or sequential logic, and that provides the function blocks with selectable output drive strength.
In particular, one embodiment of the invention has function blocks that include a logic block and a driver block. The logic block includes a plurality of disconnected gate clusters. The gate clusters can implement a wide variety of logic, including either sequential or combinational logic, simply by selecting the inputs to the respective gate clusters through customized routing. In addition, in one embodiment, the logic block includes a driver group that includes a plurality of drivers. The driver group can be programmed to produce a selected output drive strength. Such programming is mask programming (e.g., customized routing) in one embodiment.
In addition, the function blocks also include a driver block. In one embodiment the driver block also includes a driver group, including a second plurality of drivers, that can be programmed to produce a second selected output drive strength.
In some embodiments, each function block includes a ratio of logic blocks to driver blocks, for instance 4:1 or 2:1.
An embodiment in accordance with the invention will provide tremendous flexibility to the ASIC user including flexibility in that each function block can be used for combinational logic, sequential logic, or a combination of both, as well as flexibility in selecting output drive strength. Further, because an embodiment of the invention is a module based array that is largely predesigned, customization (mask programming) can be done rapidly.